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mc145149 motorola 1
interfaces with dualmodulus prescalers the mc145149 contains two pll frequency synthesizers which share a common serial data port and common reference oscillator. the device contains two 14stage r counters, two 10stage n counters, and two 7stage a counters. all six counters are fully programmable through a serial port. the divide ratios are latched into the appropriate counter latch according to the last data bits (control bits) entered. when combined with external lowpass filters and voltage controlled oscillators (vcos), the mc145149 can provide all the remaining functions for two pll frequency synthesizers operating up to the device's frequency limit. for higher vco frequency operation, a down mixer or dualmodulus prescaler can be used between the vco and the synthesizer ic. ? low power consumption through use of cmos technology ? wide operating voltage range: 3 to 9 v ? operating temperature range: 40 to + 85 c ? r range = 3 to 16,383 ? n range = 3 to 1023 ? a range = 0 to 127 ? two alinearizedo threestate digital phase detectors with no dead zone ? two lock detect signals (ld1 and ld2) ? two opendrain port expander outputs (sw1 and sw2) ? compatible with the serial peripheral interface (spi) on cmos mcus order this document by mc145149/d
semiconductor technical data p suffix plastic dip case 738 dw suffix sog package case 751d ordering information MC145149P plastic dip mc145149dw sog package 20 1 20 1 clk f in1 enb mc1 ld1 ld2 mc2 s/r out f in2 data 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 osc out sw1 v dd1 pd out1 v ss1 v ss2 pd out2 v dd2 sw2 osc in pin assignment ? motorola, inc. 1995
mc145149 motorola 2 clk data 6 5 pll2 pll1 sw1 17 sw2 14 10 10 7 7 14 14 10 10 7 7 14 14 8 2bit control s/r 7 10bit s/r 7bit s/r a counter latch 10bit n counter 7bit a counter modulus control 2 (mc2) 9 12 10 lock detect 14bit r counter 1bit latch 1bit control s/r reference counter latch control logic phase detector n counter latch 14bit shift register 16 15 4 enb 3 10bit s/r 7bit s/r a counter latch 10bit n counter 7bit a counter modulus control 1 (mc1) 2 19 1 lock detect 14bit r counter 1bit latch 1bit control s/r reference counter latch control logic phase detector n counter latch 14bit shift register osc in osc out f in1 f in2 s/r out pd out2 f r pin 13 = v dd2 pin 11 = v ss2 pd out1 f r pin 18 = v dd1 pin 20 = v ss1 block diagram f v f v ld2 ld1
mc145149 motorola 3 maximum ratings* (voltages referenced to v ss ) symbol rating value unit v dd dc supply voltage 0.5 to + 10 v v in , v out input or output voltage (dc or transient) except sw1, sw2 0.5 to v dd + 0.5 v v out output voltage (dc or transient) e sw1, sw2 0.5 to 15 v i in , i out input or output current (dc or transient), per pin 10 ma i dd , i ss supply current, v dd or v ss pins 30 ma p d power dissipation, per package2 500 mw t stg storage temperature 65 to + 150 c t l lead temperature (8second soldering) 260 c * maximum ratings are those values beyond which damage to the device may occur. 2power dissipation temperature derating: plastic dip: 12 mw/ c from 65 to 85 c sog package: 7 mw/ c from 65 to 85 c electrical characteristics (voltages referenced to v ss ) sbl ch i i v dd 40 c 25 c 85 c ui symbol characteristic v dd v min max min max min max unit v dd power supply voltage range e 3 9 3 9 3 9 v v ol output voltage 0 level v in = 0 v or v dd i out = 0 m a 3 5 9 e e e 0.05 0.05 0.05 e e e 0.05 0.05 0.05 e e e 0.05 0.05 0.05 v v oh 1 level 3 5 9 2.95 4.95 8.95 e e e 2.95 4.95 8.95 e e e 2.95 4.95 8.95 e e e v il input voltage 0 level v out = 0.5 v or v dd 0.5 v (all outputs except osc out ) 3 5 9 e e e 0.9 1.5 2.7 e e e 0.9 1.5 2.7 e e e 0.9 1.5 2.7 v v ih 1 level 3 5 9 2.1 3.5 6.3 e e e 2.1 3.5 6.3 e e e 2.1 3.5 6.3 e e e i oh output current e mc1, mc2 v out = 2.7 v source v out = 4.6 v v out = 8.5 v 3 5 9 0.60 0.90 1.50 e e e 0.50 0.75 1.25 e e e 0.30 0.50 0.80 e e e ma i ol v out = 0.3 v sink v out = 0.4 v v out = 0.5 v 3 5 9 1.30 1.90 3.80 e e e 1.10 1.70 3.30 e e e 0.66 1.08 2.10 e e e i ol output current e sw1, sw2 v out = 0.3 v sink v out = 0.4 v v out = 0.5 v 3 5 9 0.80 1.50 3.50 e e e 0.48 0.90 2.10 e e e 0.24 0.45 1.50 e e e ma i oh output current e other outputs v out = 2.7 v source v out = 4.6 v v out = 8.5 v 3 5 9 0.44 0.64 1.30 e e e 0.35 0.51 1.00 e e e 0.22 0.36 0.70 e e e ma i ol v out = 0.3 v sink v out = 0.4 v v out = 0.5 v 3 5 9 0.44 0.64 1.30 e e e 0.35 0.51 1.00 e e e 0.22 0.36 0.70 e e e i in input current e data, clk, enb 9 e 0.3 e 0.1 e 1.0 m a i in input current e f in , osc in 9 e 50 e 25 e 22 m a (continued) this device contains circuitry to protect against damage due to high static voltages or electric fields, however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper opera- tion, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd except sw1 and sw2 which may range up to 15 v. unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs should be left floating.
mc145149 motorola 4 electrical characteristics (continued) sbl ch i i v dd 40 c 25 c 85 c ui symbol characteristic v dd v min max min max min max unit c in input capacitance e e 10 e 10 e 10 pf c out threestate output capacitance e pd out e e 10 e 10 e 10 pf i dd quiescent current v in = 0 v or v dd i out = 0 m a 3 5 9 e e e 800 1200 1600 e e e 800 1200 1600 e 1600 2400 3200 m a i oz threestate leakage current e pd out v out = 0 v or 9 v 9 e 0.3 e 0.1 e 3.0 m a i oz offstate leakage current e sw1, sw2 v out = 9 v 9 e 0.3 e 0.1 e 3.0 m a switching characteristics (t a = 25 c, c l = 50 pf) symbol characteristic figure no. v dd v min max unit t tlh output rise time, mc1 and mc2 1, 6 3 5 9 e e e 115 60 40 ns t thl output fall time, mc1 and mc2 1, 6 3 5 9 e e e 60 34 30 ns t tlh , t thl output rise and fall time, ld and s/r out 1, 6 3 5 9 e e e 140 80 60 ns t plh , t phl propagation delay time, f in to mc1 or mc2 2, 6 3 5 9 e e e 125 80 50 ns t su setup time, data to clk 3 3 5 9 30 20 18 e e e ns t su setup time, clk to enb 3 3 5 9 70 32 25 e e e ns t h hold time, clk to data 3 3 5 9 12 12 15 e e e ns t rec recovery time, enb to clk 3 3 5 9 5 10 20 e e e ns t r , t f input rise and fall times, any input 4 3 5 9 e e e 5 2 0.5 m s t w input pulse width, enb and clk 5 3 5 9 40 35 25 e e e ns
mc145149 motorola 5 frequency characteristics (voltages referenced to v ss , c l = 50 pf, input t r = t f = 10 ns unless otherwise indicated) sbl p t c di i v dd 40 c 25 c 85 c ui symbol parameter test conditions v dd v min max min max min max unit f i input frequency (f in , osc in ) r 8, a 0, n 8 v in = 500 mv pp ac coupled sine wave 3 5 9 e e e 6 15 15 e e e 6 15 15 e e e 6 15 15 mhz r 8, a 0, n 8 v in = v dd to v ss dc coupled square wave 3 5 9 e e e 6 15 15 e e e 6 15 15 e e e 6 15 15 mhz switching waveforms 10% 90% any output t tlh t thl mc 50% 50% t plh t phl v dd v ss f in figure 1. 50% 50% last clk previous data latched first clk enb clk data 50% v dd v ss v dd v ss v dd v ss t su t su t rec t h 10% 90% any input v dd v ss t f t r 50% enb, clk v dd v ss t w output device under test c l * figure 2. figure 3. figure 4. figure 5. figure 6. * includes all probe and fixture capacitance.
mc145149 motorola 6 pin descriptions input pins osc in , osc out reference oscillator input/output (pins 15, 16) these pins form a reference oscillator when connected to terminals of an external parallelresonant crystal. fre- quencysetting capacitors of appropriate value must be con- nected from osc in and osc out to ground. osc in may also serve as input for an externallygenerated reference signal. the signal is typically ac coupled to osc in , but for signals with cmos logic levels, dc coupling may be used. when used with an external reference, osc out should be left open. f in1 , f in2 frequency inputs (pins 4, 7) input frequency from an external vco output. each rising edge signal on f in1 decrements the n counter, and when ap- propriate, the a counter of pll 1. similarly, f in2 decrements the counters of pll 2. these inputs have inverters biased on the linear region which allows ac coupling for signals as low as 500 mv pp. with square wave signals which swing from v ss to v dd , dc coupling may be used. data, clk data, clock inputs (pins 5, 6) shift register data and clock inputs. each lowtohigh transition on the clock pin shifts one bit of data into the on chip shift registers. refer to figure 7 for the following discus- sion. the last bit entered is a steering bit that determines which set of latches are activated. a logic high selects the latches for pll 1. a logic low selects pll 2. the secondtolast bit controls the appropriate port ex- pander output, sw1 or sw2. a logic low forces the output low. a logic high forces the output to the highimpedance state. the thirdtolast bit determines which storage latch is acti- vated. a logic low selects the a and n counter latches. a logic high selects the reference counter latch. when writing to either set of a and n counter latches, 20 clock cycles are typically used. however, if a byte oriented mcu is utilized, 24 clock cycles may be used with the first 4 bits being adon't care.o when writing to either reference counter latch, 17 clock cycles are typically used. however, if a byteoriented mcu is utilized, 24 clock cycles may be used with the first 7 bits being adon't careo. enb latch enable input (pin 3) a positive pulse on this input transfers data from the shift registers to the selected latches, as determined by the con- trol and steering data bits. a logic low level on this pin allows the user to shift data into the shift registers without affecting the data in the latches or counters. enable is normally held low and is pulsed high to transfer data into the latches. output pins pd out1 , pd out2 singleended phase detector outputs (pins 19, 12) each singleended (threestate) phase detector output produces a loop error signal that is used with a loop filter to control a vco (see figure 8). frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: highimped- ance state s/r out shift register output (pin 8) this output can be connected to an external shift register to provide band switching or control information. s/r out may also be used to check the counter programming bit stream. mc1, mc2 modulus control outputs (pins 2, 9) each output generates a signal by the onchip control logic circuitry for controlling an external dualmodulus prescaler. the modulus control level is low at the beginning of a count cycle and remains low until the a counter has counted down from its programmed value. at this time, modulus control goes high and remains high until the n counter has counted the rest of the way down from its programmed value (na additional counts since both n and a are counting down during the first portion of the cycle). modulus control is then set back low, the counters are preset to their respective programmed values, and the above sequence is repeated. this provides for a total program- mable divide value (n t ) = n ? p + a where p and p + 1 repre- sent the dualmodulus prescaler divide values respectively for high and low modulus control levels, n the number pro- grammed into the n counter, and a the number pro- grammed into the a counter. note that when a prescaler is needed, the dualmodulus version offers a distinct advantage. the dualmodulus prescaler allows a higher reference frequency at the phase detector input, increasing system performance capability, and simplifying the loop filter design. ld1, ld2 lock detect signals (pins 1, 10) each output is essentially at a high logic level when the corresponding loop is locked (f r and f v of the same phase and frequency). each output pulses low when the corre- sponding loop is out of lock (see figure 8). sw1, sw2 latched opendrain switch outputs (pins 17, 14) the state of each output is controlled by the asw stateo bit shown in figure 7. if the bit is a logic high, the correspond- ing sw output assumes the highimpedance state. if the bit is low, the sw output goes low. to control output sw1, steering bit pll 1/pll 2 shown in figure 7 must be high. to control sw2, bit pll 1/pll 2 must be low. these outputs have an output voltage range of v ss to 15 v.
mc145149 motorola 7 power supply pins v dd1 , v dd2 positive power supply (pins 18, 13) the most positive power supply potentials. both of these pins are connected to the substrate of the chip. therefore, both must be tied to the same voltage potential. this poten- tial may range from 3 to 9 v with respect to the v ss pins. for optimum performance, v dd1 should be bypassed to v ss1 and v dd2 bypassed to v ss2 . that is, two separate bypass capacitors should be utilized. v ss1 , v ss2 negative power supply (pins 20, 11) the most negative power supply potentials. both of these pins should be tied to ground. figure 7. bit stream formats r a n last bit into shift register last bit into shift register pll 1/pll 2 sw state low or a0o lsb msb lsb pll 1/pll 2 sw state high or a1o lsb msb msb note: the pd output state is equal to either v dd or v ss when active. when not active, the output is high impedance and the voltage at that pin is determined by the lowpass filter capacitor. f r reference (osc r) f v feedback (f in n) pd out ld figure 8. phase detector/lock detector output waveforms
mc145149 motorola 8 f(s) = z = w n = a) nr 1 c r 1 sc + 1 definitions: n = total division ratio in feedback loop k f (phase detector gain) = v dd /4 p for pd out k vco (vco gain) = 2 pd f vco d v vco damping factor: z 1 1 c vco pd out n w n 2k f k vco f(s) = z = w n = b) (r 1 +r 2 )sc + 1 r 2 sc + 1 c vco r 2 pd out r 1 r 1 nc(r 1 + r 2 ) r 2 c+ n k f k vco 0.5 w n k f k vco k f k vco recommended reading: gardner, floyd m., phaselock techniques (second edition). new york, wileyinterscience, 1979. manassewitsch, vadim, frequency synthesizers: theory and design (second edition). new york, wileyinterscience, 1980. blanchard, alain, phaselocked loops: application to coherent receiver design. new york, wileyinterscience, 1976. egan, william f., frequency synthesis by phase lock. new york, wileyinterscience, 1981. rohde, ulrich l., digital pll frequency synthesizers theory and design. englewood cliffs, nj, prenticehall, 1983. berlin, howard m., design of phaselocked loop circuits, with experiments. indianapolis, howard w. sams and co., 1978. kinley, harold, the pll synthesizer cookbook. blue ridge summit, pa, tab books, 1980. an535, phaselocked loop design fundamentals, motorola semiconductor products, inc., 1970. ar254, phaselocked loop design articles, motorola semiconductor products, inc., reprinted with permission from electronic design, 1987. for a typical design w n (natural frequency) 2 p fr 10 (at phase detector input). figure 9. phaselocked loop lowpass filter design design considerations crystal oscillator considerations the following options may be considered to provide a ref- erence frequency to motorola's cmos frequency synthe- sizers. use of a hybrid crystal oscillator commercially available temperaturecompensate crystal oscillators (tcxos) or crystalcontrolled data clock oscilla- tors provide very stable reference frequencies. an oscillator capable of sinking and sourcing 50 m a at cmos logic levels may be direct or dc coupled to osc in . in general, the highest frequency capability is obtained utilizing a directcoupled square wave having a railtorail (v dd to v ss ) voltage swing. if the oscillator does not have cmos logic levels on the outputs, capacitive or ac coupling to osc in may be used. osc out , an unbuffered output, should be left floating. for additional information about tcxos and data clock oscillators, please consult the latest version of the eem elec- tronic engineers master catalog, the gold book, or similar publications. design an offchip reference the user may design an offchip crystal oscillator using ics specifically developed for crystal oscillator applications, such as the mc12061 mecl device. the reference signal from the mecl device is ac coupled to osc in . for large am- plitude signals (standard cmos logic levels), dc coupling is used. osc out , an unbuffered output, should be left floating. in general, the highest frequency capability is obtained with a directcoupled square wave having railtorail voltage swing. use of the onchip oscillator circuitry the onchip amplifier (a digital inverter) along with an ap- propriate crystal may be used to provide a reference source frequency. a fundamental mode crystal, parallel resonant at
mc145149 motorola 9 the desired operating frequency, should be connected as shown in figure 10. for v dd = 5.0 v, the crystal should be specified for a load- ing capacitance, c l , which does not exceed 32 pf for fre- quencies to approximately 8 mhz, 20 pf for frequencies in the area of 8 to 15 mhz, and 10 pf for higher frequencies. these are guidelines that provide a reasonable compromise between ic capacitance, drive capability, swamping varia- tions in stray and ic input/output capacitance, and realistic c l values. the shunt load capacitance, c l , presented across the crystal can be estimated to be: c l = c in c out c in + c out + c a + c o + c1 ? c2 c1 + c2 where c in = 5 pf (see figure 11) c out = 6 pf (see figure 11) c a = 1 pf (see figure 11) c o = the crystal's holder capacitance (see figure 12) c1 and c2 = external capacitors (see figure 10) the oscillator can be atrimmedo onfrequency by making a portion or all of c1 variable. the crystal and associated com- ponents must be located as close as possible to the osc in and osc out pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. in some cases, stray capacitance should be added to the value for c in and c out . power is dissipated in the effective series resistance of the crystal, r e , in figure 12. the drive level specified by the crys- tal manufacturer is the maximum stress that a crystal can withstand without damaging or excessive shift in frequency. r1 in figure 10 limits the drive level. the use of r1 may not be necessary in some cases (i.e., r1 = 0 w ). to verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a func- tion of voltage at osc out . (care should be taken to minimize loading.) the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal will de- crease in frequency or become unstable with an increase in supply voltage. the operating supply voltage must be re- duced or r1 must be increased in value if the overdriven condition exists. the user should note that the oscillator startup time is proportional to the value of r1. through the process of supplying crystals for use with cmos inverters, many crystal manufacturers have devel- oped expertise in cmos oscillator design with crystals. dis- cussions with such manufacturers can prove very helpful (see table 1). figure 10. pierce crystal oscillator circuit r1* osc out c2 c1 r f frequency synthesizer * may be deleted in certain cases. see text. osc in figure 11. parasitic capacitances of the amplifier c in c out c a note: values are supplied by crystal manufacturer (parallel resonant crystal). 2 1 2 1 2 1 r s l s c s r e x e c o figure 12. equivalent crystal networks recommended reading technical note tn24, statek corp. technical note tn7, statek corp. e. hafner, athe piezoelectric crystal unit definitions and method of measuremento, proc. ieee, vol. 57, no. 2 feb., 1969. d. kemper, l. rosine, aquartz crystals for frequency controlo, electrotechnology , june, 1969. p. j. ottowitz, aa guide to crystal selectiono, electronic design , may, 1966. table 1. partial list of crystal manufacturers name address phone united states crystal corp. crystek crystal statek corp. 3605 mccart ave., ft. worth, tx 76110 2351 crystal dr., ft. myers, fl 33907 512 n. main st., orange, ca 92668 (817) 9213013 (813) 9362109 (714) 6397810 note: motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers.
mc145149 motorola 10 dualmodulus prescaling overview the technique of dualmodulus prescaling is well estab- lished as a method of achieving high performance frequency synthesizer operation at high frequencies. basically, the approach allows relatively lowfrequency programmable counters to be used as highfrequency programmable counters with speed capability of several hundred mhz. this is possible without the sacrifice in system resolution and per- formance that results if a fixed (singlemodulus) divider is used for the prescaler. in dualmodulus prescaling, the lower speed counters must be uniquely configured. special control logic is nec- essary to select the divide value p or p + 1 in the prescaler for the required amount of time (see modulus control defi- nition). motorola's dualmodulus frequency synthesizers contain this feature and can be used with a variety of dual modulus prescalers to allow speed, complexity, and cost to be tailored to the system requirements. prescalers having p, p + 1 divide values in the range of 3/ 4 to 128/ 129 can be controlled by most motorola frequency synthesizers. several dualmodulus prescaler approaches suitable for use with the mc145149 are: mc12009 mc12011 mc12013 mc12015 mc12016 mc12017 mc12018 mc12022a mc12032a 5/ 6 8/ 9 10 / 11 32 / 33 40 / 41 64 / 65 128 / 129 64 / 65 or 128 / 129 64 / 65 or 128 / 129 440 mhz 500 mhz 500 mhz 225 mhz 225 mhz 225 mhz 520 mhz 1.1 ghz 2.0 ghz design guidelines the system total divide value, n total (n t ) will be dictated by the application, i.e., n t = frequency into the prescaler frequency into the phase detector = n p + a n is the number programmed into the n counter, a is the number programmed into the a counter, p and p + 1 are the two selectable divide ratios available in the dualmodu- lus prescalers. to have a range of n t values in sequence, the a counter is programmed from 0 through p 1 for a particular value n in the n counter. n is then incremented to n + 1 and the a is sequenced from 0 through p 1 again. there are minimum and maximum values that can be achieved for n t . these values are a function of p and the size of the n and a counters. the constraint n a always applies. if a max = p 1, then n min p 1. then n tmin = (p 1) p + a or (p 1) p since a is free to assume the value of 0. n tmax = n max p + a max to maximize system frequency capability, the dualmodu- lus prescaler output must go from low to high after each group of p or p + 1 input cycles. the prescaler should divide by p when its modulus control line is high and by p + 1 when its modulus control is low. for the maximum frequency into the prescaler (f vco max), the value used for p must be large enough such that: 1. f vco max divided by p may not exceed the frequency capability of f in (input to the n and a counters). 2. the period of f vco divided by p must be greater than the sum of the times: a. propagation delay through the dualmodulus prescaler. b. prescaler setup or release time relative to its modulus control signal. c. propagation time from f in to the modulus control output for the frequency synthesizer device. a sometimes useful simplification in the programming code can be achieved by choosing the values for p of 8, 16, 32, or 64. for these cases, the desired value of n t results when n t in binary is used as the program code to the n and a counters treated in the following manner: 1. assume the a counter contains aao bits where 2 a p. 2. always program all higher order a counter bits above aao to 0. 3. assume the n counter and the a counter (with all the higher order bits above aao ignored) combined into a single binary counter of n + a bits in length (n = number of divider stages in the n counter). the msb of this ahy- potheticalo counter is to correspond to the msb of n and the lsb is to correspond to the lsb of a. the sys- tem divide value, n t , now results when the value of n t in binary is used to program the anewo n + a bit counter. by using the two devices, several dualmodulus values are achievable. mc device b device a device b mc12009 mc12011 mc12013 device a mc10131 mc10138 mc10154 20/ 21 50/ 51 40/ 41 or 80/ 81 64/ 65 or 128/ 129 32/ 33 80/ 81 40/ 41 100/ 101 80/ 81 note: mc12009, mc12011, and mc12013 are pin equivalent. mc12015, mc12016, and mc12017 are pin equivalent.
mc145149 motorola 11 package dimensions p suffix plastic dip case 73803 1.070 0.260 0.180 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.008 0.110 0 0.020 25.66 6.10 3.81 0.39 1.27 0.21 2.80 0 0.51 27.17 6.60 4.57 0.55 1.77 0.38 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. -a- c k n e gf d 20 pl j 20 pl l m -t- seating plane 110 11 20 0.25 (0.010) t a m m 0.25 (0.010) t b m m b d suffix sog package case 751d04 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029
mc145149 motorola 12 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters can and do vary in different applications. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmfax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mc145149/d ?

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